1. Field of the Disclosure
The present disclosure relates generally to electronic devices, and more particularly, to accessing memory of data processor devices.
2. Description of the Related Art
Data processor cores generally include an instruction execution pipeline that includes various stages that control execution of instructions. One stage of the instruction execution pipeline provides instruction information, such as effective address input operands, to a load/store unit that uses the instruction information to determine a target memory location to be accessed. Information is retrieved from (read) the target memory in response to a load request and provided to (written) the target memory location response to a store request.
Certain types of instructions, referred to herein as specialized instructions, need to have their corresponding load and store requests manipulated in a specialized manner that not only implements the primary read and write functions of a respective load or store request, but also implements special handling of the request. Two examples, of specialized instructions include atomic instructions, which require one or more memory accesses be completed in an uninterrupted manner, and decorated instructions, which cause a data access to be manipulated in a particular manner in addition to implementing its primary function. Execution of an atomic instruction results in a corresponding atomic access request being provided to the load/store unit, while execution of a decorated access instruction results in a corresponding atomic access request being provided to the load/store unit. The additional hardware overhead needed by a data processor core to implement the specialized handling needed by specialized instructions can increase the size of the data processor core. In addition, implementation of specialized requests, such as atomic requests, at a data processor core can result in the in bus locking operations, or other delays, that can affect subsequent accesses to a memory location. This delay can be especially problematic when it prevents access to information stored at a local memory of a data processor core that is needed to complete the execution of other instructions.